Exemplary embodiments of the present invention relate to a semiconductor fabrication technology, and more particularly, to a semiconductor device having buried gates and a method for fabricating the semiconductor device.
As a semiconductor device shrinks in size, it is difficult to realize diverse device characteristics and semiconductor fabrication processes. In particular, under the design rule of 40 nm, the semiconductor device meets with limitations in the fabrication technology of forming a gate structure, a bit line structure, and a contact structure. Although the semiconductor device is normally formed in those structures, it is also difficult to secure desired device characteristics in terms of resistance characteristic, refresh characteristic, low failure characteristic, and breakdown voltage characteristic. Accordingly, the semiconductor device is introduced to a buried gate process which forms gates buried in active regions. The buried gate process may decrease parasitic capacitance and increase process margins, and a smaller cell transistor may be formed thereby.
However, if the distance between a buried gate and a junction region is narrow in a buried gate structure, the electric field is raised and leakage current increases. After all, the device characteristics, particularly with respect to reliability, such as refresh time (tREF) may be degraded.
Therefore, it is desired to keep a certain distance between a buried gate and a junction region.